Many existing computer systems utilize the peripheral component interconnect (PCI) technology. PCI is a high-speed system bus specification that provides 32-bit or 64-bit data paths at 33 MHz or 66 MHz clock rates, depending upon the chip sets used.
The PCI bus is a system bus that can be populated with adapters requiring fast access to memory or each other. The PCI bus is a bus-mastered architecture. A bus-mastered approach allows for a single bus master which controls the bus and generally a single target device for any given transaction. One advantage of the PCI bus over other technologies is that the length of a burst transfer is negotiated by master and target rather than limited to a finite number of words.
The PCI bus uses burst mode to read and write data to and from adapters. Data is transferred every clock cycle, as opposed to very other clock cycle as is the case in some other bus designs. The PCI bus can provide up to 132 Mbits/sec performance during burst mode operation for 32-bit systems, and up to 264 Mbits/sec performance during burst mode operation for 64-bit systems.
The PCI bus is configured so that it is not directly connected to the processor and memory. The reason for this is that bus designs that are wired directly to the processor are limited in the number of devices they can support, usually three. The PCI bus however can support up to ten or more devices.
In normal use, a PCI host bridge (or bus controller chip or module) is connected between the central processing unit (CPU) and the PCI busses. Among other things, the bridge acts as a buffer between the CPU and the PCI busses and also maintains the PCI bus in synch with the CPU.
A problem encountered with certain PCI chip sets occurs when a user attempts to assert a warm boot on the computer system. In particular, when a warm boot is generated, for example by entering Ctrl-Alt-Delete, certain PCI chip sets, such as the Intel 440FX PCIset, do not generate a warm boot signal. Because of this, when a warm boot occurs, the data that is already in the PCI registers and buffers does not reset, but rather continues to be transferred to and from the destination port. This can lead to corrupt data files.